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The Hamburg
VHDL archive		 Welcome to the Hamburg VHDL archive! We intend to provide a collection of free, i.e. public-domain or shareware, VHDL documentation, models, and tools.

This service is provided and maintained by group TAMS, Faculty of Informatics, University of Hamburg.

Feedback We are ever looking for additional documents, models, tools and Internet links to improve this server. All contributions, hints, and corrections are welcome. Please contact Norman Hendrich or Andreas Mäder.

Please consider to contribute some of your own models and tools to the VHDL-community in turn for any information downloaded from one of the free VHDL servers.
Internet VHDL
and Resources		 The following list represents our (subjective) selection of VHDL and EDA/CAD related WWW and ftp-servers. Most public-domain or free VHDL stuff can be found there. For more addresses, try one of the WWW search-engines.
VIUF The WWW-server of the VHDL International (VI) Users' Forum (VIUF).
EDA.ORG The EDA Industry Working Groups WWW-server, with links to the VHDL working groups, VHDL resources, IEEE standards, International Conferences ...
The working groups provide additional information on specialized topics and drafts:
P1076 VHDL Analysis and Standardization Group
P1076a Shared Variable Working Group
P1076.1 Analog and Mixed-Signal Extensions to VHDL
P1076.2 VHDL Math Package
P1076.3 VHDL Synthesis Working Group
P1076.4 VHDL Initiative Towards ASIC Libraries
P1076.5 VHDL Library Utility Working Group
P1076.6 VHDL Synthesis Interoperability Working Group
oovhdl Object Oriented VHDL
vhdlpli VHDL Programming Language Interface
libieee VHDL Library
vhdl-mw VHDL Microwave Extensions
FMF The Free Model Foundation provides free VITAL compliant VHDL models.
comp.lang.vhdl The only VHDL related Usenet newsgroup. Unfortunately, with sub-average signal-to-noise ratio on some topics.
RASSP The excellent VHDL server from the RASSP project.
thor.ece.uc.edu VHDL and CAD/EDA server of the University of California.
cs.utwente.nl VHDL and CAD/EDA server at the university of Twente.
erm1.u-strasbg.fr Server of the ERM/PHASE team at the E.N.S.P.S. (University of Strasbourg), with a search engine for their collection of free VHDL models.
http://www.fp.fmv.se/vhdl/vhdl.html A server in Sweden.
OpenCores From the OpenCores missions statement: 'OPENCORES.ORG is a repository of open source, free IP synthesizable blocks and supplemental prototype boards. Most of our cores are currently under development but some are already available.'
VHDL-AMS
P1076.1 Working group: Analog and Mixed-Signal Extensions to VHDL
The first address for VHDL-AMS.
VHDL-AMS.de Some VHDL-AMS references, server under construction...
Southampton VHDL-AMS Validation Suite, Models and Examples
VHDL FAQ The four parts FAQ collection of the comp.lang.vhdl newsgroup, which is reposted about monthly. The most recent version can be obtained from the VHDL International server. The FAQ ist also available in PDF format for printing.

The links below are to local copies of the FAQ on our server, which are not updated on a regular basis: Part 1, Part 2, Part 3, Part 4, PAL FAQ
Documentation This section presents VHDL documentation of all sort - textbooks, tutorials, tool descriptions, etc.:
VHDL cookbook The yet classical introduction into VHDL and hardware design by Peter J. Ashenden. It presents the complete description of a non-pipelined 32-bit microprocessor. The link is to our local copy of the PDF version of the book. See ftp://ftp.cs.adelaide.edu.au/pub/VHDL-Cookbook/ for the cookbook homepage.
VHDL Kompakt
new		 An introduction to VHDL in German with small design examples and lots of syntax diagrams (what statement is allowed where) by Andreas Mäder (592K PDF file).

The previous version: "VHDL Kurzbeschreibung" (238K compressed Postscript file).

Schaltungsdesign
mit VHDL		 An introduction to VHDL 1987/1993 simulation and synthesis in German, originally published as a book by Franzis Verlag. Now available in PDF format for free (personal use).
Amontec VHDL memo Browsable syntax (VHDL'87) with additional context information and small examples.
VHDL: an introduction An elementary introduction to VHDL, written as his master's thesis by Francis Bruno, in chapters: Also by Francis Bruno, a VHDL tutorial: VHDL Representations of some hardware architectures, a basic computer and an assembler:
 
VHDL verification course Introduction to VHDL simulation together with some utility VHDL source code. Covers topics from basic testbenches to file I/O, signal monitors, checking of timing-constraints, etc. Also gives hints to scripting, file organization, and test strategy.
VHDL Online The University of Erlangen (Germany) offers an online VHDL tutorial course in English or German. Given a fast-enough Internet connection, it is also possible to remote-use the examples - design and simulate - using the SpeedCHART and SYNOPSYS tools. Cool!

To use the tools, you have to register (and pay), but the course material and models are free. They also offer a CD-ROM with the complete material.

 
Style guides A selection of VHDL style and modelling guides:
VHDL modelling guide The ESA (European Space Agency) guidelines for VHDL modelling. Presents the modelling style required for ESA design qualification with lots of useful tricks and conventions (65K compressed Postscript).
The VHDL Standard The ESA VHDL status report. An overview of activities, organizations and European tool efforts (127K compressed Postscript).
VHDL modelling guide US Navy 'Standard Hardware and Reliability Program' (SHARP) Technology Independent Representation of Electronic Products (TIREP) report. Available as 541K compressed Unix .tar.gz archive or in individual chapters:
 
VHDL-AMS Information related to the IEEE 1076.1 Standard
VHDL-AMS Tutorial
new		 Analog and Mixed-Signal Modeling Using the VHDL-AMS Language
Excellent tutorial, from the DAC'99 (673K PDF, 199 pages)
 
EDA-tools Howto's and recipes for commercial VHDL simulators and VLSI design tools
ModelSim 'Step by Step' online-tutorial for Mentor Graphics ModelSim, including lab examples. Synthesis with Leonardo Spectrum is also covered within the documentation.
online-doc Our online-documentation about the Synopsys DC tools, Cadence NC-Simulator and Cadence DFII (schematic- and layout-editor) in combination with AMS or Atmel CMOS design kits (in German).
A complete list of tools installed at our institite is here - for questions on these tools contact Andreas Mäder.
Papers A collection of several VHDL related technical reports and conference papers.

This section is obviously not complete. Please submit your papers!

Recursive and repetitive VHDL modelling Peter J. Ashenden: Recursive and repetitive VHDL modelling. Discusses recursive and iterative structure descriptions for both VHDL-87 and VHDL-93 (117K compressed Postscript).
The corresponding models are available here (53K ASCII).
BABEL machine W. Hans, J.J. Ruz, F. Sįenz, S. Winkler: A VHDL Specification of a Shared Memory Parallel Machine for Babel (60 pages, 128K compressed Postscript).
Femto-VHDL John Van Tassel: Femto-VHDL: The semantics of a subset of VHDL and its embedding in the HOL theorem-prover. (479K compressed Postscript tar, or individual chapters) PhD dissertation, University of Cambridge
VHDL quality checking The VLSI-group of the Universidad politecnica de Madrid has some papers about VHDL design flow and automatically checking the quality of VHDL code.
Verification Some papers about verification and model checking using VHDL tools:
Draft Standard Proposals Here you can find some material from the different VHDL Working Groups - draft material and standard proposals. Notice, that these are not the official standards, therefore refer to
P1076 Draft IEEE Standard VHDL - Language Reference Manual
P1076.4 VITAL (VHDL initiative towards ASIC libraries) drafts, modelling guidelines and requirements:
P1076.6 VHDL Synthesis Syntax Reference and vendor documentation:
Models and Packages Our collection of public-domain VHDL models and packages. If you cannot find a model here, please make sure to check the other VHDL servers listed on top of this page.
 
Packages Standardized packages, as part of the IEEE Standards, are not free and have to be bought from the above address. The following packages are either draft standards and proposals from the working groups or free (vendor specific) packages. Please see and respect the copyright notice inside the files.

Before download, please check your tool- or vendor-specific documentation, since most tools have the standard packages already included. Often they use specialized versions, which are optimized with respect to the internal algorithms.

IEEE 1164
  • std_logic_1164 data types, definitions and functions, v4.200, 01/02/92
  • std_logic_1164 proposed extensions for 1076-93 language, v4.300, 08/07/95
To have an arithmetic defined, other packages have to be used: either the package numeric_std from the IEEE Standard 1076.3 (recommended method) or vendor specific packages, like the ones from Synopsys:
P1076.2
P1076.4
C/UNIX functions
new		 A package that implements several useful functions from the C standard library in VHDL, provided by the CAD group at Case Western Reserve University under GPL license. The package includes string processing functions like strcpy, I/O functions like printf or fgetc, and even some regular expression matching functions, which allows to quickly develop testbenches.
 
Microprocessors
SoftCores
new		 A private website with four synthesizable microprocessor cores: PPX16 (PIC16C55, PIC16F84), T80 (Z80), T51 (8051), and AX8 (90S1200, 90S2313). The site also offers some utilities, including a converter from Intel Hex and Motorola S-Record files to VHDL ROM descriptions, and a tool to read and write synchronous serial (I2S) data to files.
HC11 core Both behavioural and RTL source code for the HC11 microcontroller core from Green Mountain Computing Systems. Not surprinsingly, makefiles and project files are optimized for their own VHDL simulator.
8051 MCU
new		 A new 8051 MCU IP core under LGPL license, co-developed by Oregano Systems and the University of Wien. The model is synthesizable, fully synchronous, and includes timer and UART interfaces.
mc8051 Both behavioural and structural (synthesizable) models of the 8051 µController, with memory blocks but without peripherial devices. The model comes with testbench and several .hex files.
i8051 Another synthesizable model of the 8051 µController core (without interrupt handling). Includes ROM and RAM blocks but no peripheral devices. The model comes with several test programs.
PIC 16C5x A structural model of the PIC16C5x microcontroller under the GNU public license from Ernesto Romani (romani@ascu.unian.it). The model has been synthesized to a Xilinx 4005 FPGA and comes together with a tool to convert assembler code to a VHDL ROM model.

compressed tar archive (267K, structural VHDL model, assembly packer, some documentation)

Check http://www.microchip.com/ for datasheets, documentation, and (free) tools for the PIC series of microcontrollers.

ERC32
(SPARC V7)		 A VHDL simulation model of the ERC32, a radiation tolerant SPARC processor for space applications, complete with documentation and makefiles for the Synopsys and Model Tech simulators.

All models are fully functional with parametrisable timing. The source code and data sheets for the models are provided for free (GNU license) via the ERC32 home page: ERC32 WWW-Server.

The processor consists of integer unit, floating-point unit and memory controller. IU and FPU are compatible with the Cypress 76C01 and 76C02 Sparc V7 processors.

LEON
(SPARC V8)		 The LEON processor is a synthesizable implementation of the SPARC-V8 architecture, distributed under the LGPL license. The processor includes a five-stage integer pipeline and an AMBA-style bus with several peripherial blocks. The LEON source code is also an interesting example of using VHDL data types and generics for model configuration. The processor has been sythesized to several target libraries, as well as Altera and Xilinx FPGAs.
DLX Both behavioral and RT-level model of Hennessy and Patterson's generic 32bit RISC-processor architecture (without instruction pipeline, however).
compressed tar archive (37K, VHDL description and two simple programs).
directory with the uncompressed files.
SuperScalar DLX SuperScalar DLX:
A PPC603-style superscalar mixed behaviour/RTL model of the DLX processor from the TU Darmstadt, Germany:
  • superscalar, pipelined implementation of DLX (but without floating-point)
  • 4 separate functional untis: branch-resolve, arithmetic-logical, multiply-divide, load-store
  • 5-entry reorder buffer, up to 5 active instructions
  • 4-entry branch-target-buffer
  • precise exceptions
  • small 64-entry I-cache and D-cache
The link above contains documentation, all VHDL models, and some test programs in ZIP format. The VHDL code itself is nicely commented and very readable.
GL85 GL85: This circuit is an op-code compatible clone of the i8085 8-bit microprocessor:
6502 A behavioural (but synthesizable) model of the 6502 microprocessor from the Free-IP site.
i80386 A simple (and incomplete) behavioral model of the Intel 80386 microprocessor (58K ASCII).
m68000 A simple (and incomplete) behavioral model of the Motorola 68000 microprocessor (36K ASCII).
AMD 2901 AMD 2901 bit slice(Unix .tar.gz)
AMD 2910 bit slice(Unix .tar.gz)
 
Memory
SRAM, full timing Our generic SRAM model with full timing, by A. Klindworth. The model uses generic parameters for timing and size, timing checks, startup initialization from file, memory dump to file, etc.
SRAM, no timing A simple model of a 64Kx8 SRAM without timing, but with startup initialization from a file.
DRAM A DRAM model by Shannon Hill (posted to comp.lang.vhdl)
EPROM, no timing A simple 64Kx8 EPROM model without timing checks, but with an Intel-HEX file parser for initialization.
Vendor memory models Today, several memory vendors offer VHDL simulation models for their products. For example, Micron Technology offers downloadable (but licensed) simulation models for several memory products, including double data rate SDRAM and SGRAM.
 
Misc. & Cores Note that some of the files listed in this section are demo versions or behavioural versions of otherwise commercial products. They are listed here among fully free software because they implement important and useful cores - e.g. PCI or USB controllers.
Jane neural network processor VHDL and Verilog sources for a programmable neural network processor by Suresh Kumar. The download consists of a ~2MByte archive file which contains the source files and documentation. See the "Guide/About.html" file in the archive file for an overview.
EuCore PCI-M32 Downloadable VHDL source core for free evaluation of a PCI core from Maxlock. You can download the documentation for free, but have to register with them to get the code to decrypt the VHDL sources. Professional use requires a project licence, see here.
USB core While the (synthesizable) USB controller core itself is a commercial product, Trenz electronic provides the behavioural model and testbenches under GNU licence for free (see the "free downloads" link.) They also offer a clone of the MCS51 microcontroller.
AMCC5933 A bus functional model of the "PCI Matchmaker" chip from AMCC. It models the local interface so that you can simulate reads and writes to the local interface as if they were coming from the PCI bus. Timing check are included along with single transfers and burst transfers.
Free-DES A synthesizable core for DES encryption from the Free-IP site.
CRC LFSR A cyclic-redundancy-check feedback shift-register, by Russ DeHoedt (posted to comp.lang.vhdl)
MCNC circuits The standard CAD-benchmark circuits of the MCNC (ftp.mcnc.org).
FPGA course A collection of circuits and testbenches for our recent FPGA lab. course, which uses Altera FPGAs. For example, you will find another SRAM model and a component to convert ASCII-strings into RS232 (8N1) format. Irdafuse is a circuit to protect an IrDA tranceiver from accidental overload during testing of student's designs.
FFT A synthesizable model of a FFT generator together with a full description (420KB PDF). From the author's submission mail: The design of the processor was taken from an IEEE workshop report. The report detailed a 256-point FFT I have limited mine to an 8-point FFT for easier debugging, which obviously cannot be used as such, since its accuracy would be poor. Neverthless all the features of the processor are present and upgrading it to a 256 point processor is easy.
VHDL-Tools Our collection of public-domain VHDL tools. If you cannot find a tool here, please make sure to check the other VHDL servers listed on top of this page.
 
Grammar and Parsers
VHDL-93 Hyperlinked BNF of the VHDL-93 BNF grammar. Or get the ASCII version.
VHDL grammar VHDL lex/yacc grammar (20K compressed ASCII).
VAUL VHDL Analyzer and Utility Library (VAUL) parser home page at the University of Dortmund. VAUL is written in C++ and needs flex/bison.
our local but outdated copy (University of Hamburg) (520K tar.gz).
VHDL-93 parser in Prolog A VHDL-93 compliant parser written in SWI-Prolog with (experimental) VHDL-93 design description browser (gziped tar archive), Readme
VHDL lex/yacc parser VHDL parser vhdl-lexyacc.1.4 by Thomas Dettmers (19K compressed tar).
VHDL parser in Java VHDLParser and VHDLTree: a GNU licensed VHDL parser and parse-tree viewer written in Java.
VHDL parser VHDL parser vhdl-rexlalr.1.2 from the University of Twente, based on the GMD Compiler Tool Box CCTB (35K compressed tar).

Parser frontend vhdlfront.1.1 (100K compressed tar).

VHDL Object Model Parser A parser written in the REFINE system, Ohio Board of Regents and the University of Cincinnati (36K compressed tar), individual files.
vhdl2vl A GPL'ed converter from VHDL to Verilog
vhdl-2-c A prototype VHDL-2-C compiler (for sequential statements).
 
Simulator
VHDL Simili A VHDL'93 compiler and simulator from Symphony EDA for Windows and Linux platforms. The "command line mode" compiler and simulator are available for free download. A complete version, with GUI and waveform viewer, is licensed for an evaluation period of 21 days.
BlueHDL Restricted but free demo version of the VHDL/Verilog simulator for Windows and Linux from from Blue Pacific Computing, Inc. From their website: the free Student Versions are limited to 20k bytes of source code (about 1000 lines), 100 internal signals and 4k events per signal.
ivsim A free VHDL simulator from Korea! Check the following link for a short README about download, installation, and usage of the tools.
Alliance The Alliance CAD system (Universite de Paris) includes the only free VHDL simulator available. However, only a very small subset of VHDL is supported. The system comes with source code, and can be ftp'd from:
FreeHDL project A project to develop a free, open source, GPL'ed VHDL simulator for Linux! The goal of the project is to develop a VHDL-93 compliant simulator with graphical waveform viewer, source level debugger, and with commercial quality.

While some of the parser, simulator and tool code is already available, the project is still looking for new members and supporters!

 
Waveform Viewer
GTKWave Powerful waveform viewer for various output formats (VCD/EVCD/LXT/Synopsys), based on GTK+ toolkit. Current versions are developped and maintained by the AMULET Group, while previous versions and links to Win32 implementations can be found at the 1.3.x GTKWave page.
 
Editors
Emacs VHDL mode The official Emacs VHDL mode home page. The mode includes syntax highlighting, indentation, templation insertion, word completion, customized menus, ... everything.
vim Newer versions of vim, a freeware vi clone, also include support support and syntax highlighting for VHDL.
VHDL editor with hierarchy tree A Tcl-based VHDL editor with syntax highlighting and a separate "explorer" style hierarchy browser, which also allows to quickly jump to a selected VHDL object (e.g. architecture).
nedit A freeware Unix editor with syntax highlighting for several programming languages, including VHDL.
PRISM editor An editor for Windows 95/98/NT with support for VHDL and several other languages, e.g. ABEL and Synopsys scripts. The editor is shareware; it will disable features after a trial period. The corresponding Windows based help file is free.
 
Pretty Printing
mvp_v11 Make VHDL Pretty utility. (69K compressed tar).
MVPx A Windows frontend for MVP. Generates formatted Postscript from VHDL source code.
vhdl-nice The pretty printer of Michael Knieser (version 0.1c).
vhdl2html A vhdl to HTML converter by Michael Knieser.
 
Misc
TimingTool TimingTool is a free graphical timing diagram editor, implemented as a Java applet. The editor uses TDML (timing diagram modelling language) as its data format and supports export to VHDL, Verilog, and text/graphics formats. As timing diagrams are stored on the TimingTool server, a user account with corresponding registration is required.
Ardid Ardid is a set of tools developed at the University of Madrid to help in the VHDL design flow of systems on silicon. It provides both a graphical front-end environment optimized for a VHDL design flow, and a set of tools to automatically check quality aspects of VHDL code. Ardid itself is free, but the tools rely on a commercial VHDL parser, which requires a licence. More details can be found in the papers about Ardid.
hdl2html A perl script to convert VHDL or Verilog into HTML code with color highlighting of keywords etc.
vsplit A tool to split design files into individual files for each entity, architecture, configuration (12K compressed tar).
vmkr A makefile generator (version 2.8) to be used in combination with vsplit (110K compressed tar).
blif2vhdl A BLIF to VHDL converter (51K compressed tar, with SunOS, Solaris, and Linux binaries. Source code (C++) included).
Brusey20 A FSM-schematic to VHDL code generator, with C sources (the MSC thesis of Thomas C. Mayo) The tool takes xfig drawings of FSMs and generates synthesizable VHDL code:
Impressum
04.06.2003
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